-- 寄存器-并入串出
-- 设计一个8位的并入串出的数据转换电路


library ieee;
use ieee.std_logic_1164.all;

entity p_in_s_out is
    port(
        din : in std_logic_vector(7 downto 0);
        clk, load : in std_logic;
        dout : out std_logic;
        dout8 : out std_logic_vector(7 downto 0);
    );
end p_in_s_out;

architecture behave of p_in_s_out is
    signal data : std_logic_vector(7 downto 0);
begin 
    
    process(clk, din) begin
        if clk'event and clk = '1' then
            if load = '1' then
                dout8 <= din;
                data <= din;
            else
                for i in 0 to 7 loop
                    data(6 downto 0) <= data(7 downto 1);   -- 移位
                    dout <= data(0);    -- loop方式输出dout
                end loop;

                -- 或者
                -- for i in 0 to 7 loop
                --     data <= data SRL 1;
                --     dout <= data(0);
                -- end loop
            end if;
        end if;
    end process;

end behave;


-- testbench
-- always进程产生时钟
always: process begin
    clk <= '1';
    wait for clk_period/2;
    clk <= '0';
    wait for clk_period/2;
end progress 
-- test进程描述激励信号，确定所有输入信号
test: process begin
    load <= '1', '0' after 50 ns;
    din <= "11110000", "10101010" after 30ns;
    wait;
end process;
